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Silicon on Insulator (SOI) Wafers

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Product Properties
Description MSC offers SOI wafers for superior control of speed, power, and electrostatics in CMOS device applications. Within SOI wafers, we have various options for thickness and uniformity. The layer stack consists of a silicon substrate (CZ/FS) at the bottom, a thick BOX layer in the middle, and a silicon device layer on the top. A variety of customizable options are available. We offer prime wafers only.

Additional information

Diameter

2”, 3”, 4”, 5”, 6”, 8”

Dopant

B, P, Undoped

Resistivity (ohm-cm)

≤1, 1-10, 10-100, 100-1k, 1k-10k, ≥10k

Orientation

100, 111

Uniformity

+/-10nm, +/-0.5um, +/-1um

Thickness (um 0.05-300)

(um; 0.05-300)

Thickness (100nm - 3 µm)

(100nm – 3 µm)

Type

CZ, FZ

Thickness (um)

200, 279, 300, 381, 400, 525, 625, 675, 725, 775

Flats/Notch

No, SEMI Primary Flat, Jeida Flat, 1 SEMI Flats, 2 SEMI Flats, 1 SEMI Notch

Lasermark (8” & 12” only)

None, SEMI M13 FRONT-SIDE MARK, SEMI M13 BACK-SIDE MARK, FRONT-SIDE & BACK-SIDE MIXED

Finish

SSP, DSP

Dopant-S

B, P, Undoped

Resistivity-S (ohm-cm)

≤1, 1-10, 10-100, 100-1k, 1k-10k, ≥10k

Orientation-S

100, 111